This invention relates generally to a semiconductor memory device such as a static type random access memory device. The invention more particularly relates to a circuit form suitable for reading out, at a high speed, data from a spare memory cell of a redundant spare memory block for replacing or masking defective memory cells in the memory device.
An earlier, exemplary, redundancy circuit form for relieving defective bits is disclosed in Japanese Patent Laid-Open Nos. 164096/1983 and 46497/1987. FIG. 2 of Japanese Patent Laid-Open No. 164096/1983 discloses a defect relieving technique of a dynamic type random access memory device using 1-transistor type memory cells. The illustration is a circuit form wherein a defective memory cell of an A mat in one of the memory blocks is activated by an address signal, and at the same time, a redundant spare memory cell of the A mat in the other memory block is activated so that only the sense amplifier in this other memory block senses a bit line voltage difference and amplifies it. However, FIG. 2 of this prior art reference teaches defect relief solely by the selective activation of sense amplifiers in the memory blocks, but does not disclose a high speed defect relieving redundancy circuit wherein the memory cell information is read outside the memory blocks.
Japanese Patent Laid-Open No. 46497/1987 similarly discloses a defect relieving technique for a dynamic type random access memory. The described circuit is of a form wherein a normal memory array and a spare memory array for relieving this normal memory array are disposed in one of the memory blocks. Another normal memory array and a similar spare memory array are disposed also in the other memory block, the operation of an address decoder for making access to the normal memory array is inhibited when an access is made to a defective memory cell in the normal memory array while the access is made to the spare memory array for relieving the normal memory array. Information from this spare memory array is read out to the outside of the memory block.
The defect relieving technique described in Japanese Patent Laid-Open No. 46497/1987 involves the steps of detecting the coincidence of a defective memory cell in the normal memory array with an address signal after the address signal is supplied from outside the memory device, inhibiting the operation of the address decoder for making access to the normal memory array on the basis of this coincidence detection then making access to the spare memory array and reading out the information from this spare memory array to the outside of the memory block. The access time relating to the read-out of the information from the spare memory for relieving defects is thereby disadvantageously slow.
The present invention remedies the aforenoted problems, and others, and is directed to provide a memory device having a reduced delay of the access time relating to the information read-out operation from the redundant spare memory.